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Section 5 Registers
5 . 1
Overview
The Q2 has address-mapped registers mapped onto the address space (H'000 to H'2FF). These
registers are divided into six groups—interface control registers, memory control registers, display
control registers, rendering control registers, input data control registers, and color palette registers.
Word access is used on all of these registers. The address specification is made by inputting the
address from pins A10 to A1 while the CS1 pin is in the 0 state.
Addresses H'026 to H'0FF are reserved, and should not be read or written to. Reading or writing to
these addresses may result in the loss of address-mapped register values, and unpredictable operation
by the Q2.
To enable the Q2 to manage UGM access rights, initial values must be set in the address-mapped
registers by the SuperH before it accesses the UGM. If the UGM is accessed without setting these
initial values, the Q2 may output a continuous wait signal to the SuperH. The setting procedure is
shown in 1 to 3 below.
1. Set the initial values in the system control register. Set SRES = 0, DRES = 1, DEN = 0.
2. Set the initial values in registers 002–025.
3. Set SRES = 0, DRES = 0.
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