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CLK0 (input)/CLKi
(multiplication off/
multiplication on)
RD (input)
R D High-Level Setup Time and Hold Time in CPU Read Cycle
Figure 6-2
6 . 2
Horizontal Display Start Position Register Value
When the DSX value is 512 or greater, if drawing or UGM access is performed during display,
noise may be generated in the range in which the number of dots in the X direction exceeds 512.
For this reason, a value that satisfies condition (1) or (2) below should be set in the horizontal
display start position register (HDS). The horizontal display start position register (HDS) value is
determined by the graphic bit mode, the internal operating frequency (CLK0), and the display dot
clock (DCLK). If the DSX value is less than 512, it is not necessary to satisfy condition (1) or
(2). Normally, GBM is set to 1 when the DSX value is 512 or greater, to extend the range within
which HDS can vary.
162
T5
T1
t
t
RDS
RDH
t
RDHW
Timing
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