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performing the access. If this is not done, the Q2 will output waits continuously when the CPU
accesses the UGM.
• Access by software
In access by software, the UGM is accessed as part of the main memory.
In a write operation, no-wait access is possible if there is empty space in the Q2's built-in 32-
byte FIFO buffer.
In a read operation, a number of wait cycles are inserted. The number of wait cycles varies
greatly depending on the relationship between the operating clock and the display dot clock, and
the screen size. For example, with a 33 MHz operating clock, a 7 MHz display dot clock, and a
320 × 240 (8 bits/pixel) screen size, the average number of wait cycles will be around 23.
• Access by DMAC
With a CPU that has a built-in DMAC (such as the SH-2 or SH704X), data in the memory
connected to the CPU can be transferred to the UGM using the DMAC. DMA transfer can be
used to transfer display list or YUV data.
Single address mode can be used in DMA transfers, since graphics memory addresses are
controlled by the Q2's built-in address counter. However, only cycle-steal mode can be used as
the bus mode.
UGM Access by Q2: EDO page mode DRAM can be connected to the Q2 as UGM. Use of
this memory enables the Q2 to perform memory access in one-cycle (operating clock) units.
The memory configuration consists of one or two 256-kword × 16-bit (4-Mbit) DRAMs, and one
or two 1-Mword × 16-bit (16-Mbit) DRAMs.
With regard to row address and column address multiplex control, it is possible to use products
with a 9, 10, 11, or 12-bit row address.
The type of memory is set in the memory mode register (MEMR)
3 . 2 . 3
Memory Map
The Q2 performs UGM address control. The UGM includes the display list area, binary source
area, work area, 8-bit/pixel source and 16-bit/pixel source areas, and 8-bit/pixel rendering and 16-
bit/pixel rendering areas. The UGM is configured in 512-byte units, and a different memory
configuration is used for each area. The memory configuration for each of the areas is shown in
figure 3-3.
Area settings are made according to the respective start addresses (see section 5.4, Memory Control
Registers).
• 1-bit/pixel (work, binary source, display list)
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