Note On Use Of Auto Display Change Mode; Note On Color Palette Register Writes During Display - Hitachi HD64411 Q2 User Manual

Quick 2d graphics renderer
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reset bit should not be set to 1 during Q2 drawing operations. After a hardware reset this bit is set
to 1, so it should be cleared to 0 before performing drawing operations with the Q2.
A dummy display list is provided to enable Q2 drawing to be aborted midway. An abort can be
performed by executing a rendering start using the dummy display list. However, invalid drawing
of 1 to 4 dots may be performed when the dummy display list is executed, depending on when
drawing is halted (because of invalid data remaining in the drawing unit). Therefore, the display
start address (in this case, the address used as the drawing start address by the Q2) and the work start
address should be adjusted before having the Q2 execute the dummy display list. This will make it
possible for invalid drawing to be performed in a UGM area which is not used by the Q2 as a
drawing area or work area, enabling invalid drawing to be prevented.
The dummy display list must include at least one of the following commands: POLYGON4A,
POLYGON4B, POLYGON4C, LINE, RLINE, PLINE, RPLINE. An example of a dummy
display list is shown below.
Example of dummy display list:
SCLIP, XMAX, YMAX
LCOFS, 0, 0
LINE, LINE COLOR, 2, 0, 0, 0, 0
TRAP
6 . 5

Note on Use of Auto Display Change Mode

When using auto display change mode, if Q2 drawing is aborted due to a frame change, invalid
drawing of 1 to 4 dots may be performed when the next display list is executed, depending on when
drawing is halted (because of invalid data remaining in the drawing unit). Adjust the display list in
the system design stage so that drawing processing is always completed before a frame change.
6 . 6

Note on Color Palette Register Writes during Display

If another register access (see relevant registers below) is to be performed directly after execution of
a color palette register write during display, this should be executed after performing a color palette
register read immediately after the color palette register write. If this processing is not executed, the
relevant register access may not be completed normally.
Relevant register addresses: 005, 008, 009, 00A, 00B, 013–01E
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