Status Register (Sr) - Hitachi HD64411 Q2 User Manual

5 . 3 . 2

Status Register (SR)

Bit: 15 14
TVR FRM
Initial value: 0 0
Read/Write: R R
Note: * Value is retained.
The status register (SR) is a 16-bit read-only register used to read the internal status of the Q2 from
outside.
SR is initialized as follows in a reset:
• Flag DBF retain their values.
• The Q flags are set to 0010.
• All other flags are cleared to 0.
Bit 15—TV Sync Signal Error Flag (TVR): Flag that indicates that EXVSYNC has
been detected within the vertical cycle.
Bit 15:
T V R Description
The rise of EXVSYNC has been detected each time within the vertical cycle
0
determined by the vertical scan cycle register (VCR) setting after the TVR flag has
been cleared by the DRES bit in SYSR or the TVCL bit in SRCR.
In TV sync mode (bits TVM1 and TVM0 = 10 in DSMR), a rise of EXVSYNC has not
1
been detected within the vertical cycle determined by the VCR set value.
The TVR flag retains its state until cleared by a reset or by software.
Bit 14—Frame Flag (FRM): Flag that indicates the vertical blanking interval after frame
display.
Bit 14:
FRM Description
0 Indicates the interval from FRM flag clearing by the DRES bit in SYSR or the FRCL bit
in SRCR until the end of the next display in non-interlace mode, or until the end of the
next even field display in interlace mode or interlace sync & video mode.
1 Indicates the interval from the first even field vertical blanking interval after FRM flag
clearing by the DRES bit in SYSR or the FRCL bit in SRCR until the FRM flag is cleared
again (frame units).
13 12 11 10 9
DMF CER VBK
TRA CSF
0 0 0 0 0
R R R R R
8 7 6 5 4
DBF
— — — —
* — — — —
R — — — —
3 2 1 0
Q3 Q2 Q1 Q0
0 0 1 0
R R R R
(Initial value)
(Initial value)
131