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Color Palette Registers H, L000–255 (CP000RH, L to CP255H, L) are 32-bit readable/writable
registers. The settings are valid when the GBM bit is 0.
The color palette is controlled in 2-word units comprising one pixel. The same units must
therefore be used for accesses to the color palette registers.
When writing to color palette registers, first write to the R register, then to the G and B registers.
The R register value is reflected as the new color palette set value when the G and B registers are
set.
When reading color palette registers, first read the R register, then the G and B registers.
When accessing color palette registers, it is not possible to access another register between the R
register and the G and B registers.
In color palette accesses, access to another Q2 register is prohibited between access to the R
register and access to the G and B registers. In modes in which GBM = 1 (16 bits/pixel), these
registers are used as part of the internal display circuitry. Therefore, color palette register set values
are lost when the GBM bit is set to 1.
For the same reason, if a color palette is accessed when GBM = 1, the color palette access will not
be completed and the Q2 will output a continuous CPU wait signal.
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