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2 . 1
Pin Arrangement and Functions
2 . 1 . 1
Overview of Pins
Figure 2 shows an overview of the Q2's pins.
MODE0–2
CLK0
CLK1
System control
RESET
CAP0
TEST
A1–A22
D0–D15
CPU (SuperH)
WE0
interface
WE1
DACK
DREQ
WAIT
GND
PLL V
Power supply
PLL GND
CPU V
CPU GND
Section 2 Pins
CS0
CS1
RD
HD64411
IRL
V
CC
(FP-144)
CC
CC
Figure 2-1
Overview of Q2 Pins
DD0–DD17
DCLK
CSYNC
FCLK
HSYNC/EXHSYNC
Display interface
VSYNC/EXVSYNC
DISP
CDE
ODDF
MA0–MA11
MD0–MD15
MWE
MRAS0
UGM interface
MRAS1
MLCAS
MUCAS
MOE
11
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