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Pins: Table 3-6 shows the Q2 pin states after a reset.
Table 3-6
Pin States After Reset
I/O pins
Input state
Output state (low-level output)
Output pins
Low-level output
High-level output
Low/high-level output
58
D0–D15, VSYNC /EXVSYNC ,
HSYNC/EXHSYNC, ODDF
MD0–MD15
DISP, CDE, DD0–DD17
DREQ , IRL , WAIT
CSYNC, DCLK, FCLK, MA0–MA11, MWE,
MRAS0 , MRAS1 , MLCAS , MUCAS, MOE
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