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Bit 13—Display Enable (DEN): These bits control starting and stopping of display
synchronous operation..
Bit 14:
Bit 13:
D R E S
D E N
0
0
1
1
0
1
Bits 12 to 10—Reserved: Only 0 should be written to these bits.
128
Description
Display operation is started.
The DRES bit cannot be cleared to 0 while the RESET pin is low. When
using the Q2 from the initial state, make all control register settings
before clearing the DRES bit to 0. When the DEN bit is 0, display data
from pins DD17 to DD0 has the value set in display off output registers H
and L (DRORH, L).
Display operation is started.
The DRES bit cannot be cleared to 0 while the RESET pin is low. When
using the Q2 from the initial state, make all control register settings, clear
the DRES bit to 0, and then set the DEN bit to 1. Display data from pins
DD17 to DD0 has the value stored in the UGM from the next frame.
Display synchronous operation is started.
The Q2 only performs UGM refresh operations, regardless of the settings
of TVM1 and TVM0 in the display mode register. With these settings, the
Q2 operates as follows: With these settings, the Q2 operates as shown
below. In a transition from DRES, DEN = 01 to DRES, DEN = 10, the
DRES, DEN setting becomes 11 temporarily for reasons relating to
internal updating, but this does not affect operation.
1. Drawing is not performed even if the RS bit is set to 1 in RS.
2. Display data from pins DD17 to DD0 is all-0 output.
3. The VBK flag is cleared to 0 in SR.
4. Waits are output continuously when a UGM access is performed by
the CPU.
Setting prohibited
(Initial value)
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