Hitachi HD64411 Q2 User Manual page 140

Bit 10—Trap Flag (TRA): Flag that indicates the end of command execution.
Bit 10:
TRA Description
0 Indicates the interval from TRA flag clearing by the SRES bit in SYSR or the TRCL bit
in SRCR until the end of execution of the next command.
1 Command execution has ended, or the current command is not being executed.
The TRA flag retains its state until cleared by a reset or by software.
Bit 9—Command Suspend Flag (CSF): Flag that indicates suspension of command
execution.
Bit 9:
C S F Description
0 Normal operation
1 A rendering end interrupt has not been generated in the interval from CSF flag clearing
by the SRES bit in SYSR or the CSCL bit in SRCR until the next frame change.
The CSF flag retains its state until cleared by a reset or by software.
Bit 8—Display Buffer Frame (DBF): Flag that indicates the display start address register
used as the display start address by the Q2.
Bit 8:
DBF Description
0 Address indicated by DSAR0 is used as display start address
1 Address indicated by DSAR1 is used as display start address
Bits 7 to 4—Reserved: These bits always read 0.
Bits 3 to 0—Q Flags (Q3 to Q0): Flags used for Q2 Series product identification.
Bit 3: Bit 2:
Q 3 Q 2
0 0
Bit 1: Bit 0:
Q 1 Q 0
1 0
Description
HD64411
(Initial value)
(Initial value)
133