7 . 5 . 1 0 Master Mode Display Timing - Hitachi HD64411 Q2 User Manual

7 . 5 . 1 0 Master Mode Display Timing

CLK1 (input)
(DOT = 0)
CLK1 (input)
(DOT = 1)
DCLK (output)
FCLK (output)
DD17 to DD0
(output)
HSYNC (output)
VSYNC (output)
ODDF (output)
CSYNC (output)
DISP (output)
CDE (output)
Figure 7-16
T1
t
DCRD
t
t FCFD
FCRD
t t
DDS DDH
t
HSDD
t
VSDD
t
ODDD
t
SYDD
t
DIDD
t
CDEDD
Master Mode Display Timing
T1 T1
t
DCRD
t
FCRD
t
HSDD
t
VSDD
t
ODDD
t
SYDD
t
DIDD
t
CDEDD
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