Rendering Mode Register (Remr) - Hitachi HD64411 Q2 User Manual

5 . 3 . 7

Rendering Mode Register (REMR)

Bit: 15 14
— —
Initial value: — —
Read/Write: — —
Note: * Value is retained.
The rendering mode register (REMR) is a 16-bit readable/writable register that specifies Q2
rendering operations.
If the value of this register is modified during a drawing operation, operation will be temporarily
unstable.
REMR bits MWX and GBM retain their values in a reset.
Bits 15 to 7—Reserved: Only 0 should be written to these bits.
Bit 6—Memory Width (MWX): Specifies the X-direction logical coordinate space of the
UGM connected to the Q2.
Bit 6:
M W X Description
0 X-direction logical coordinate space is 512 pixels
1 X-direction logical coordinate space is 1024 pixels
Bits 5 to 1—Reserved: Only 0 should be written to these bits.
Bit 0—Graphic Bit Mode (GBM): Specifies the bit configuration of the rendering data
handled by the Q2.
Bit 0:
G B M Description
0 Rendering data bit configuration is 8 bits/pixel
1 Rendering data bit configuration is 16 bits/pixel
Figure 5-3 shows the correspondence between memory physical addresses (bytes) and the
coordinates shown in the memory map example in section 3.2.3, Memory Map. The X upper
coordinate and X lower coordinate signify the values when the memory map example X value is
divided into the respective bus widths. Similarly, the Y upper coordinate and Y lower coordinate
are values obtained by dividing the Y value.
142
13 12 11 10 9
— — —
— —
— — — — —
— — — — —
8 7 6 5 4
— MWX — —
—
— — * — —
— — R/W — —
3 2 1 0
— — GBM
—
— — — *
— — — R/W