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Table 3-2 Register Settings*
Register
N o .
(Address)
Register Name
008
Display size register X (DSRX)
009
Display size register Y (DSRY)
013
Display
windows
014
015
016
017
Horizontal sync pulse width
register (HSWR)
018
Horizontal scan cycle register
(HCR)
019
Vertical sync position register
(VSPR)
01A
Vertical scan cycle register
(VCR)
Notes: 1. In all scanning modes the settings of bits VDS, VDE, VSP, and VC are made for a one-
frame unit.
2. The HDS and HDE bit specifications are the values from detection of a low EXHSYNC
level at the rise of CLK1 until the rise of DCLK after detection again at the fall of CLK1.
48
1
Bit Names
DSX
DSY
Horizontal display
HDS
start position register
(DSWR-HDS)
Horizontal display
HDE
end position register
(DSWR-HDE)
Vertical display start
VDS
position register
(DSWR-VDS)
Vertical display end
VDE
position register
(DSWR-VDE)
HSW
HC
VSP
VC
Operating
Mode
Master Mode TV Sync
Mode
5
xw-1
xw-1*
yw-1
yw-1
hsw+xs-3
hsw+xs-8*
hsw+xs-3+xw
hsw+xs-8+xw*
4
y s
ys*
ys+yw
ys+yw
hsw-1
hsw-1
hc-1
hc
vc-vsw
vc-vsw
v c
vc+2
2,
3
*
2
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