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(3) CPU Read Cycle
Table 7-6 CPU Read Cycle
I t e m
Address Setup Time
Address Hold Time
CSn Setup Time
CSn Hold Time
RD "High" Level Setup Time t
WAIT Cycle Start Time 1
RD "High" Level Width
Read Data Setup Time For
WAIT
WAIT Delay Time
RD "High" Level Hold Time
Read Data Turn On Time
Read Data Hold Time
Read Data Turn Off Time
WE "High" Level Width
Notes: 1. If the fall of CSn is later than the fall of RD , the specifications of t
are from the fall of CSn. (CSn = CS0, CS1.)
t
WEHW
2. If the rise of CSn is earlier than the rise of RD, the specifications of t
are from the rise of CSn. (CSn = CS0, CS1.)
and t
WEHW
Symbol
Min
M a x
t
0
—
ADS
t
0
—
ADH
t
0
—
CSS
t
0
—
CSH
1/2 ×
—
RDS
t
– 9
cyc0
t
—
4t
WAS1
t
t
—
RDHW
cyc0
t
10
—
RDDWS
t
—
25
WAD
12 – 1/2 ×
t
—
RDH
t
cyc0
t
0
—
RDDON
t
4
—
RDDH
t
4
—
RDDOF
t
t
—
WEHW
cyc0
T e s t
Unit
Conditions N o t e s
ns
Figure 7-6
ns
ns
ns
ns
ns
cyc0
ns
ns
ns
ns
ns
ns
ns
ns
ADS
1
2
Multiplica-
tion off
Multiplica-
tion off
, t
, t
, and
WAS1
RDDON
, t
, t
,
ADH
RDDH
RDDOF
181
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