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1. Clear the VBK bit and wait until the VBK bit is set to 1.
2. Set a value of VDE - VDS or greater in DSY. The DSY value set previously is treated as valid
internally until the next internal update is performed.
3. Set DRES = 0 and DEN = 0. When an internal update is performed, the Q2 switches to display
off mode.
The procedure for returning to the DRES = 0, DEN = 1 state from display off mode is as follows.
4. Clear the VBK bit and wait until the VBK bit is set to 1. In this way it is possible to confirm
that the internal update period has ended.
5. Set a value of VDE - VDS - 1 in DSY.
6. Set DRES = 0 and DEN = 1. When an internal update is performed, the Q2 performs display
from the address indicated by the display start address.
6 . 1 1
Note on Changing TV Synchronization Mode
When b'01 is set in the TV synchronization mode bits (TVM) in the display mode register
(DSMR) and a transition is made to synchronization system switching mode, set the display reset
bit (DRES) to 1 and clear the display enable bit (DEN) to 0 in the system control register before
making the transition to synchronization system switching mode.
This procedure provides for the HD64411 to perform UGM refreshing in synchronization system
switching mode.
The procedure is shown below. The procedure is performed in order from step 1 to 2. The
HD64411 performs UGM refreshing via internal updates.
1. Set DRES = 1 and DEN = 0.
2. Set TVM1 = 0 and TVM0 = 1.
The procedure for switching from synchronization system switching mode to TV synchronization
mode is shown in 3 to 6 below.
3. Input the clock to CLK1. When TVM1 = 1 and TVM0 = 0, also input signals to the
EXHSYNC, EXVSYNC, and ODDF pins.
4. If the display size is to be changed, set values in the Q2's address-mapped registers.
5. Set TVM1 = 0 and TVM0 = 0, or TVM1 = 1 and TVM0 = 0, to enable CLK1 pin clock input.
6. Set DRES = 0 and DEN = 1. When an internal update is performed, the Q2 begins display.
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