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Table 7-4 Input Clocks (2) (Pins MODE2 to MODE0 = 000, 001, 010:
Multiplication On)
I t e m
Symbol Min
Clock 0 Cycle Time
t
Clock 0 Cycle Time
t
Clock 0 Cycle Time
t
Clock 0 "High" Level
t
Pulse Width
Clock 0 "Low" Level
t
Pulse Width
Clock Delay Time 1
t
Clock Delay Time 2
t
Clock Delay Time 3
t
Clock Delay Time 4
t
Clock i Cycle Time
t
Clock i "High" Level
t
Pulse Width
Clock i "Low" Level
t
Pulse Width
Clock 1 Cycle Time
t
Clock 1 "High" Level
t
Pulse Width
Clock 1 "Low" Level
t
Pulse Width
Clock 1 Duty
t
Clock Rise Time
t
Clock Fall Time
t
30.3
cyc
60.6
cyc
121.2
cyc
10.1
CPWH
10.1
CPWL
—
CLKD1
—
CLKD2
—
CLKD3
—
CLKD4
30.3
cyc0
10.1
CiPWH
10.1
CiPWL
60.6
cyc1
25.3
C1PWH
25.3
C1PWL
0.5t
– 1.7
C1DT
cyc1
—
cr
—
cf
T e s t
M a x
Unit
Conditions N o t e s
50
ns
Figure 7-4
100
ns
200
ns
—
ns
—
ns
10
ns
t
/4 + 11.7
ns
cyc
t
/2 + 11.7
ns
cyc
3t
/4 + 11.7 ns
cyc
50
ns
—
ns
—
ns
150
ns
170
—
ns
—
ns
0.5t
+ 1.7
ns
cyc1
5
ns
5
ns
×1
×2
×4
XW ≥ 512
XW < 512
179
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