Hitachi HD64411 Q2 User Manual page 61

Table 3-4 Estimated Number of Refresh Cycles (for 1/60s Field)
Sample Display
Screen Sizes Memory Size
320 × 240
640 × 240
640 × 480
The Q2 supports CAS-before-RAS refresh mode.
The refresh cycles set in bits REF3–0 are executed from the fall of the DISP signal.
Display Timing: The relationship between the display control register settings and the display
signals is shown in figure 3-17.
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Number of Refresh Cycles (Per Raster)
4 Mbit × 1 4 Mbit × 2
5 5
— 5
— —
16 Mbit × 1 16 Mbit × 2
— —
5 5
3 3