Input Control Registers; Image Data Transfer Start Address Registers H And L (Isarh, Isarl) - Hitachi HD64411 Q2 User Manual

5 . 7

Input Control Registers

The input control registers comprise five 16-bit registers related to the control of input data
conversion, mapped onto addresses (A10–A1) H'021 to H'025. The settings in these registers are
valid when the setting of bits YUV1 and YUV0 in the input data conversion mode register (IEMR)
is 01 or 10.
5 . 7 . 1

Image Data Transfer Start Address Registers H and L (ISARH, ISARL)

Bit: 15 14
ISARH — —
Initial value: — —
Read/Write: — —
Bit: 15 14
ISARL
Initial value: 0 0
Read/Write: R/W R/W
Note: * Value is retained.
Image data transfer start address registers H and L (ISARH, ISARL) are 16-bit readable/writable
registers that specify the image data transfer destination as a physical address when the setting of
bits YUV1 and YUV0 is 01 or 10. The upper bits (A22 to A16) of the start address are set in the
ISAH field, and the lower bits (A15 to A1) in the ISAL field. The address indicated by the ISAH
and ISAL fields is a word address.
If the value of these registers is modified during a series of data conversion operations from the
time bits YUV1 and YUV0 are set to 01 or 10 by the CPU until YUV mode is cleared
automatically by the Q2, operation will be unstable.
Bits 15 to 7 of ISARH and bit 0 of ISARL are reserved. Only 0 should be written to these bits.
The values of the ISAH field in ISARH and the ISAL field in ISARL are initialized to all-0 by a
reset.
156
13 12 11 10 9
— — — — —
— — — — —
— — — — —
13 12 11 10 9
ISAL (address A15–A1 setting)
0 0 0 0 0
R/W R/W R/W R/W R/W
8 7 6 5 4
— — ISAH (address A22–A16 setting)
— — 0 0 0
— — R/W R/W R/W
8 7
6 5 4
0 0 0 0 0
R/W R/W R/W R/W R/W
3 2 1 0
0 0 0 0
R/W R/W R/W R/W
3 2 1 0
—
0 0 0 —
R/W R/W R/W —