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6 . 1
CPU Clock and Q2-CLK0
1. When the SuperH and Q2 are operated asynchronously, input a clock that satisfies the
following conditions to the CLK0 pin.
High level interval of RD input to Q2, and WE0 and WE1 > Q2 WE or RD setup time + hold
time + Q2 operating clock cycle (see figure 6.2).
2. When the SuperH and Q2 are operated using the same cycle, it is assumed that a clock with the
same frequency and same phase as the SuperH clock is used as the Q2 operating clock.
Therefore, Q2 multiplication should be turned off, and the clock output from the CK pin
should be input directly to CLK0 (see figure 6-1). This operation is possible only with an SH-
1 or SH-2 CPU.
The RD and WE high-level setup time and hold time specifications must still be observed
when synchronous clock operation is used (figure 6-2).
XTAL
SH-1 or SH-2
PLL: ×1
×2
×3
Figure 6-1
Section 6 Usage Notes
CK
Selection
Example of Connection for Synchronous Operation
Q2
CLK0
Multiplication off
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