Vertical Start Position Register (Vspr); Vertical Scan Cycle Register (Vcr) - Hitachi HD64411 Q2 User Manual

5 . 5 . 4

Vertical Start Position Register (VSPR)

Bit: 15 14
— —
Initial value: — —
Read/Write: — —
Note: * Value is retained.
The vertical start position register (VSPR) is a 16-bit readable/writable register that specifies the
vertical sync signal start position in raster-line units. In TV sync mode (bits TVM1 and TVM0 set
to 10 in DSMR), this register setting must be made so that the VSYNC fall setting position
specified by this register is the same as or later than the fall of EXVSYNC .
Bits 15 to 10 of VSPR are reserved. Only 0 should be written to these bits (a read will return an
undefined value).
VSPR bits VSP retain their values in a reset.
5 . 5 . 5

Vertical Scan Cycle Register (VCR)

Bit: 15 14
— —
Initial value: — —
Read/Write: — —
Note: * Value is retained.
The vertical scan cycle register (VCR) is a 16-bit readable/writable register that specifies the
vertical scan interval, including the vertical retrace line interval, in raster-line units. In TV sync
mode (bits TVM1 and TVM0 set to 10 in DSMR), the EXVSYNC rise detection time limit
should be set. If a rise is not detected within the time limit, the result is indicated by the TVR flag
in SR.
Bits 15 to 10 of VCR are reserved. Only 0 should be written to these bits (a read will return an
undefined value).
VCR bits VC retain their values in a reset.
152
13 12 11 10 9
— — —
— VSP
— — — — *
— — — — R/W
13 12 11 10 9
— — — — VC
— — — — *
— — — — R/W
8 7 6 5 4
VSP VSP VSP VSP VSP
* * * * *
R/W R/W R/W R/W R/W
8 7 6 5 4
VC VC VC VC VC
* * * * *
R/W R/W R/W R/W R/W
3 2 1 0
VSP VSP VSP VSP
* * * *
R/W R/W R/W R/W
3 2 1 0
VC VC VC VC
* * * *
R/W R/W R/W R/W