Display Start Address Registers 0 And 1 (Dsar0, Dsar1) - Hitachi HD64411 Q2 User Manual

5 . 4 . 2

Display Start Address Registers 0 and 1 (DSAR0, DSAR1)

Bit: 15 14
DSAR0 — —
Initial value: — —
Read/Write: — —
Bit: 15 14
— —
DSAR1
Initial value: — —
Read/Write: — —
Note: * Value is retained.
Display address registers 0 and 1 (DSAR0, DSAR1) are 16-bit readable/writable registers that
specify the memory areas to be used as UGM frame buffers.
Only the upper 6 bits (A22 to A16) of the start physical address of frame buffer 0 (F0) are set in
the DSA0 field in DSAR0, and only the upper 6 bits (A22 to A16) of the start physical address of
frame buffer 1 (F1) are set in the DSA1 field in DSAR1.
The display start address register whose contents are actually valid as the display start address is the
register indicated by DBF in SR. The display start address register whose contents are not valid as
the display start address indicates the rendering coordinate origin. When these registers are modified,
the new set value becomes valid when an internal update is performed in the case of the display
start address register whose contents are valid as the display start address, and when an external
update (rewrite) is performed in the case of the display start address register that indicates the
rendering coordinate origin.
Bits 15 to 7 of DSAR0 and DSAR1 are reserved. Only 0 should be written to these bits (a read
will return an undefined value).
The DSA0 field in DSAR0 and the DSAR1 field in DSAR1 retain their values in a reset.
146
13 12 11 10 9
— — — — —
— — — — —
— — — — —
13 12 11 10 9
— — — — —
— — — — —
— — — — —
8 7 6 5 4
— —
DSA0 (address A22–A16 setting)
— — * * *
— — R/W R/W R/W
8 7 6 5 4
— — DSA1 (address A22–A16 setting)
— — * * *
— — R/W R/W R/W
3 2 1 0
* * * *
R/W R/W R/W R/W
3 2 0
1
* * * *
R/W R/W R/W R/W