Dma Register Map; Table 48. Dma Register Map And Reset Values - ST STM32F101xx Reference Manual

RM0034
10.4.7

DMA register map

The following table gives the DMA register map and the reset values.
Table 48. DMA register map and reset values
Offset Register
DMA_ISR
0x000
Reset value
DMA_IFCR
0x004
Reset value
DMA_CCR1
0x008
Reset value
DMA_CNDTR1
0x00C
Reset value
DMA_CPAR1
0x010
Reset value 0
DMA_CMAR1
0x014
Reset value 0
0x018
DMA_CCR2
0x01C
Reset value
DMA_CNDTR2
0x020
Reset value
DMA_CPAR2
0x024
Reset value 0
DMA_CMAR2
0x028
Reset value 0
0x02C
DMA_CCR3
0x030
Reset value
DMA_CNDTR3
0x034
Reset value
DMA_CPAR3
0x038
Reset value 0
DMA_CMAR3
0x03C
Reset value 0
0x040
DMA_CCR4
0x044
Reset value
DMA_CNDTR4
0x048
Reset value
Reserved
0 0 0 0 0
Reserved
0 0 0 0 0
Reserved
Reserved
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
Reserved
Reserved
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
Reserved
Reserved
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
Reserved
Reserved
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0
0 0
PA[31:0]
0 0 0 0 0 0 0 0 0
MA[31:0]
0 0 0 0 0 0 0 0 0
Reserved
0
0 0
PA[31:0]
0 0 0 0 0 0 0 0 0
MA[31:0]
0 0 0 0 0 0 0 0 0
Reserved
0
0 0
PA[31:0]
0 0 0 0 0 0 0 0 0
MA[31:0]
0 0 0 0 0 0 0 0 0
Reserved
0
0 0
DMA controller (DMA)
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
M PSIZ
PL
SIZE E
[1:0]
[1:0] [1:0]
0 0 0 0 0 0 0 0 0
NDT[15:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
M PSIZ
PL
SIZE E
[1:0]
[1:0] [1:0]
0 0 0 0 0 0 0 0 0
NDT[15:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
M PSIZ
PL
SIZE E
[1:0]
[1:0] [1:0]
0 0 0 0 0 0 0 0 0
NDT[15:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
M PSIZ
PL
SIZE E
[1:0]
[1:0] [1:0]
0 0 0 0 0 0 0 0 0
NDT[15:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
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