Figure 320. Ethernet Mac Remote Wakeup Frame Filter Register (Eth_Macrwuffr) - ST STM32F101xx Reference Manual

RM0034

Figure 320. Ethernet MAC remote wakeup frame filter register (ETH_MACRWUFFR)

Wakeup frame filter reg0
Wakeup frame filter reg1
Wakeup frame filter reg2
Wakeup frame filter reg3
Wakeup frame filter reg4
Wakeup frame filter reg5
Wakeup frame filter reg6
Wakeup frame filter reg7
Ethernet MAC PMT control and status register (ETH_MACPMTCSR)
Address offset: 0x002C
Reset value: 0x0000 0000
The ETH_MACPMTCSR programs the request wakeup events and monitors the wakeup
events.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
rs
Bit 31 WFFRPR: Wakeup frame filter register pointer reset
When set, it resets the Remote wakeup frame filter register pointer to 0b000. It is automatically
cleared after 1 clock cycle.
Bits 30:10 Reserved
Bit 9 GU: Global unicast
When set, it enables any unicast packet filtered by the MAC (DAF) address recognition to be a
wakeup frame.
Bits 8:7 Reserved
Bit 6 WFR: Wakeup frame received
When set, this bit indicates the power management event was generated due to reception of a
wakeup frame. This bit is cleared by a read into this register.
Bit 5 MPR: Magic packet received
When set, this bit indicates the power management event was generated by the reception of a
Magic Packet. This bit is cleared by a read into this register.
Bits 4:3 Reserved
Bit 2 WFE: Wakeup frame enable
When set, this bit enables the generation of a power management event due to wakeup frame
reception.
Ethernet (ETH): media access control (MAC) with DMA controller
Filter 3
RSVD RSVD
Command
Filter 3 Offset
Filter 1 CRC - 16
Filter 3 CRC - 16
Reserved
Res.
Filter 0 Byte Mask
Filter 1 Byte Mask
Filter 2 Byte Mask
Filter 3 Byte Mask
Filter 2
RSVD
Command
Filter 2 Offset Filter 1 Offset
9 8
rw
Filter 1 Filter 0
RSVD
Command Command
Filter 0 Offset
Filter 0 CRC - 16
Filter 2 CRC - 16
ai15648
7 6 5 4 3 2 1
rc_ rc_
rw rw
r r
891/959
0
rs