ST STM32F101xx Reference Manual page 726

USB on-the-go full-speed (OTG_FS)
Bit 1 PCDET: Port connect detected
The core sets this bit when a device connection is detected to trigger an interrupt to the
application using the Host port interrupt bit in the Core interrupt register (HPRTINT bit in
OTG_FS_GINTSTS). The application must write a 1 to this bit to clear the interrupt.
Bit 0 PCSTS: Port connect status
0: No device is attached to the port
1: A device is attached to the port
OTG_FS host channel-x characteristics register (OTG_FS_HCCHARx)
(x = 0..7, where x = Channel_number)
Address offset: 0x500 + (Channel_number × 0x20)
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
DAD
rs rs rw rw rw rw rw rw rw rw
Bit 31 CHENA: Channel enable
This field is set by the application and cleared by the OTG host.
Bit 30 CHDIS: Channel disable
The application sets this bit to stop transmitting/receiving data on a channel, even before the
transfer for that channel is complete. The application must wait for the Channel disabled
interrupt before treating the channel as disabled.
Bit 29 ODDFRM: Odd frame
This field is set (reset) by the application to indicate that the OTG host must perform a transfer
in an odd frame. This field is applicable for only periodic (isochronous and interrupt)
transactions.
Bits 28:22 DAD: Device address
This field selects the specific device serving as the data source or sink.
Bits 21:20 Reserved
Bits 19:18 EPTYP: Endpoint type
Indicates the transfer type selected.
Bit 17 LSDEV: Low-speed device
This field is set by the application to indicate that this channel is communicating to a low-
speed device.
Bit 16 Reserved
726/813
rw rw rw
0: Channel disabled
1: Channel enabled
0: Even frame
1: Odd frame
00: Control
01: Isochronous
10: Bulk
11: Interrupt
9
EPNUM
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
RM0034
8 7 6 5 4 3 2
MPSIZ
1 0