ST STM32F101xx Reference Manual page 904

Ethernet (ETH): media access control (MAC) with DMA controller
Ethernet PTP time stamp high register (ETH_PTPTSHR)
Address offset: 0x0708
Reset value: 0x0000 0000
This register contains the most significant (higher) 32 time bits. This read-only register
contains the seconds system time value. The Time stamp high register, along with Time
stamp low register, indicates the current value of the system time maintained by the MAC.
Though it is updated on a continuous basis.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
r r r r r r r
Bits 31:0 STS: System time second
The value in this field indicates the current value in seconds of the System Time maintained by
the core.
Ethernet PTP time stamp low register (ETH_PTPTSLR)
Address offset: 0x070C
Reset value: 0x0000 0000
This register contains the least significant (lower) 32 time bits. This read-only register
contains the subsecond system time value.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
r r r r r r
Bit 31 STPNS: System time positive or negative sign
Bits 30:0 STSS: System time subseconds
904/959
r r r r r r
r r r r r r r
This bit indicates a positive or negative time value. When set, the bit indicates that time
representation is negative. When cleared, it indicates that time representation is positive.
Because the system time should always be positive, this bit is normally zero.
The value in this field has the subsecond time representation, with 0.46 ns accuracy.
STS
r r r r r r r
STSS
r r r r r r r
9 8 7 6 5
r r r r r r r
9 8 7 6 5
r r r r r r r
RM0034
4 3 2 1 0
r r r r r
4 3 2 1 0
r r r r r