ST STM32F101xx Reference Manual page 706

USB on-the-go full-speed (OTG_FS)
Bits [2:0] TOCAL: FS timeout calibration
The number of PHY clocks that the application programs in this field is added to the full-speed
interpacket timeout duration in the core to account for any additional delays introduced by the
PHY. This can be required, because the delay introduced by the PHY in generating the line
state condition can vary from one PHY to another.
The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The
application must program this field based on the speed of enumeration. The number of bit
times added per PHY clock is 0.25 bit times.
OTG_FS reset register (OTG_FS_GRSTCTL)
Address offset: 0x10
Reset value: 0x2000 0000
The application uses this register to reset various hardware features inside the core.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
r
Bit 31 AHBIDL: AHB master idle
Indicates that the AHB master state machine is in the Idle condition.
Note: Accessible in both Device and Host modes.
Bits 30:11 Reserved
Bits 10:6 TXFNUM: TxFIFO number
This is the FIFO number that must be flushed using the TxFIFO Flush bit. This field must not be
changed until the core clears the TxFIFO Flush bit.
...
Note: Accessible in both Device and Host modes.
Bit 5 TXFFLSH: TxFIFO flush
This bit selectively flushes a single or all transmit FIFOs, but cannot do so if the core is in the
midst of a transaction.
The application must write this bit only after checking that the core is neither writing to the
TxFIFO nor reading from the TxFIFO. Verify using these registers:
Read—NAK Effective Interrupt ensures the core is not reading from the FIFO
Write—AHBIDL bit in OTG_FS_GRSTCTL ensures the core is not writing anything to the
FIFO.
Note: Accessible in both Device and Host modes.
706/813
Reserved
00000:
– Non-periodic TxFIFO flush in Host mode
– Tx FIFO 0 flush in Device mode
00001:
– Periodic TxFIFO flush in Host mode
– TXFIFO 1 flush in device mode
00010: TXFIFO 2 flush in device mode
00101: TXFIFO 15 flush in device mode
10000: Flush all the transmit FIFOs in device or host mode.
9 8 7 6 5 4 3
TXFNUM
rw rs rs
RM0034
2 1 0
rs rs rs