Capture/Compare Channels; Figure 122. Control Circuit In External Clock Mode 2; Figure 123. Capture/Compare Channel (Example: Channel 1 Input Stage) - ST STM32F101xx Reference Manual

Arm-based 32-bit mcus

Hide thumbs Also See for STM32F101xx:

Table of Contents

Capture/compare channels

Each Capture/Compare channel is built around a capture/compare register (including a

shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and

an output stage (with comparator and output control).

The following figure gives an overview of one Capture/Compare channel.

The input stage samples the corresponding TIx input to generate a filtered signal TIxF.

Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be

used as trigger input by the slave mode controller or as the capture command. It is

prescaled before the capture register (ICxPS).

The output stage generates an intermediate waveform which is then used for reference:

OCxRef (active high). The polarity acts at the end of the chain.

Counter clock = CK_CNT = CK_PSC

Counter register

TI1F_Falling

(from channel 2)

TI2F_falling

(from channel 2)

General-purpose timer (TIMx)

to the slave mode controller

/1, /2, /4, /8

(from slave mode

Do you have a question about the STM32F101xx and is the answer not in the manual?