Precision Time Protocol (Ieee1588 Ptp) - ST STM32F101xx Reference Manual

RM0034
1. Disable the Transmit DMA (if applicable) and wait for any previous frame transmissions
to complete. These transmissions can be detected when Transmit Interrupt
(ETH_DMASR register[0]) is received.
2. Disable the MAC transmitter and MAC receiver by clearing the appropriate bits in the
MAC configuration register.
3. Wait until the Receive DMA empties all the frames from the Rx FIFO.
4. Enable Power-down mode by appropriately configuring the PMT registers.
5. Enable the MAC Receiver and enter Power-down mode.
6. Turn-off the application and transmit clock inputs to the core (and other relevant clocks
in the system) to reduce power and enter Sleep mode.
7. On receiving a valid wakeup frame, the Ethernet peripheral exits Power-down mode.
8. On receiving the interrupt, the system must enable the application and transmit clock
inputs to the Ethernet.
9. Read the ETH_MACPMTCSR register to clear the interrupt, then enable the MAC and
resume normal operation.
28.5.9

Precision time protocol (IEEE1588 PTP)

The IEEE 1588 standard defines a protocol that allows precise clock synchronization in
measurement and control systems implemented with technologies such as network
communication, local computing and distributed objects. The protocol applies to systems
that communicate by local area networks supporting multicast messaging, including (but not
limited to) Ethernet. This protocol is used to synchronize heterogeneous systems that
include clocks of varying inherent precision, resolution and stability. The protocol supports
system-wide synchronization accuracy in the submicrosecond range with minimum network
and local clock computing resources. The message-based protocol, known as the precision
time protocol (PTP), is transported over UDP/IP. The system or network is classified into
Master and Slave nodes for distributing the timing/clock information. The protocol's
technique for synchronizing a slave node to a master node by exchanging PTP messages is
described in
Ethernet (ETH): media access control (MAC) with DMA controller
Figure 307.
849/959