Figure 265. Host-Mode Fifo Address Mapping And Ahb Fifo Access Mapping - ST STM32F101xx Reference Manual

RM0034
Within the controller:
Read access to any one of the 4 KB regions is mapped to the RxFIFO
Write operations to any non-periodic IN endpoint or OUT channel are mapped to the
non-periodic TxFIFO
In Host mode, write operations to any periodic OUT channel are mapped to the
common periodic TxFIFO
In Device mode, write access to one of the IN endpoints is mapped to the
corresponding endpoint Tx FIFO (bits 30:27 in the Device endpoint control register map
an endpoint to a specific device Tx FIFO)

Figure 265. Host-mode FIFO address mapping and AHB FIFO access mapping

Any periodic channel
DFIFO push access
Any non-periodic
channel DFIFO push
access from AHB
Any channel DFIFO pop
access from AHB
Periodic Tx
FIFO control
from AHB
(optional)
MAC pop
Non-periodic
Tx FIFO control
MAC pop
Rx FIFO control
MAC push
USB on-the-go full-speed (OTG_FS)
Single data
FIFO
Periodic Tx packets
Periodic Tx packets
Rx packets
HPTXFSIZ[31:16]
HPTXFSIZ[15:0]
NPTXFSIZ[31:16]
NPTXFSIZ[15:0]
RXFSIZ[31:16]
Rx start address
fixed to 0
A1 = 0
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