Figure 272. Receive Fifo Read Task - ST STM32F101xx Reference Manual

Arm-based 32-bit mcus
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RM0034

Figure 272. Receive FIFO read task

Bulk and control OUT/SETUP transactions
A typical bulk or control OUT/SETUP pipelined transaction-level operation is shown in
Figure
273. See channel 1 (ch_1). Two bulk OUT packets are transmitted. A control SETUP
transaction operates in the same way but has only one packet. The assumptions are:
The application is attempting to send two maximum-packet-size packets (transfer
size = 1, 024 bytes).
The non-periodic transmit FIFO can hold two packets (128 KB for FS).
The non-periodic request queue depth = 4.
Normal bulk and control OUT/SETUP operations
The sequence of operations in
No
Unmask RXFLVL
interrupt
Read the received
packet from the
OTG_FS_GRXSTSP
Receive FIFO
Yes
Figure 273
OTG_FS programming model
Start
RXFLVL
interrupt ?
Yes
Mask RXFLVL
Unmask RXFLVL
interrupt
interrupt
Read
PKTSTS
No
0b0010?
Yes
BCNT > 0?
(channel 1) is as follows:
No
ai15674
771/959

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