Table 99. Fsmc_Tcrx Bit Fields - ST STM32F101xx Reference Manual

Arm-based 32-bit mcus
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RM0034
Table 98.
Bit No.
11
10
9
8
7
6
5-4
3-2
1
0
Table 99.
Bit No.
27-24
23-20
19-16
15-8
7-4
3-0
FSMC_BCRx bit fields (continued)
Bit name
WAITCFG
to be set according to memory
WRAPMOD
to be set according to memory
WAITPOL
to be set according to memory
BURSTEN
0x1
FWPRLVL
Set to protect memory from accidental write access
FACCEN
Set according to memory support
MWID
As needed
MTYP
0x1 or 0x2
MUXEN
As needed
MBKEN
0x1
FSMC_TCRx bit fields
Bit name
DATLAT
Data latency
0x0 to get CLK = HCLK (not supported)
CLKDIV
0x1 to get CLK = 2 × HCLK
BUSTURN
no effect
DATAST
no effect
ADDHLD
no effect
ADDSET
no effect
Flexible static memory controller (FSMC)
Value to set
Value to set
427/959

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