ST STM32F101xx Reference Manual page 900

Ethernet (ETH): media access control (MAC) with DMA controller
Ethernet MMC transmit interrupt mask register (ETH_MMCTIMR)
Address offset: 0x0110
Reset value: 0x0000 0000
The Ethernet MMC transmit interrupt mask register maintains the masks for interrupts
generated when the transmit statistic counters reach half their maximum value. (MSB of the
counter is set). It is a 32-bit wide register.
31 30 29 28 27 26 25 24 23 22
Reserved
Bits 31:22 Reserved
Bit 21 TGFM: Transmitted good frames mask
Setting this bit masks the interrupt when the transmitted, good frames, counter reaches half
the maximum value.
Bits 20:16 Reserved
Bit 15 TGFMSCM: Transmitted good frames more single collision mask
Setting this bit masks the interrupt when the transmitted good frames after more than a single
collision counter reaches half the maximum value.
Bit 14 TGFSCM: Transmitted good frames single collision mask
Setting this bit masks the interrupt when the transmitted good frames after a single collision
counter reaches half the maximum value.
Bits 13:0 Reserved
Ethernet MMC transmitted good frames after a single collision counter
register (ETH_MMCTGFSCCR)
Address offset: 0x014C
Reset value: 0x0000 0000
This register contains the number of successfully transmitted frames after a single collision
in Half-duplex mode.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
r r r r r r r
Bits 31:0 TGFSCC: Transmitted good frames single collision counter
Transmitted good frames after a single collision counter.
900/959
21 20 19 18 17 16
Reserved
rc_r
r r r r r r r
15 14 13 12 11 10
rc_r rc_r
TGFSCC
r r r r r r r
9 8 7 6 5 4
Reserved
9 8 7 6 5 4
r r r r r r r
RM0034
3 2 1 0
3 2 1 0
r r r r