Figure 66. Counter Timing Diagram, Internal Clock Divided By 4, Timx_Arr=0X36; Figure 67. Counter Timing Diagram, Internal Clock Divided By N; Figure 68. Counter Timing Diagram, Update Event With Arpe=1 (Counter Underflow) - ST STM32F101xx Reference Manual

RM0034

Figure 66. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36

Note: Here, center-aligned mode 2 or 3 is used with an UIF on overflow

Figure 67. Counter timing diagram, internal clock divided by N

Figure 68. Counter timing diagram, update event with ARPE=1 (counter underflow)

CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
CK_PSC
Timer clock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
CK_PSC
CEN
Timer clock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload preload register
Write a new value in TIMx_ARR
Auto-reload active register
Advanced-control timers (TIM1&TIM8)
0034
0035
20 1F 01
06 05 04 03 02 01 00 01 02 03 04 05 06 07
FD
FD
0036 0035
00
36
36
257/959