ST STM32F101xx Reference Manual page 878

Ethernet (ETH): media access control (MAC) with DMA controller
RDES1: Receive descriptor Word1
31 30 29 28 27 26 25
RBS2
rw rw rw rw rw rw rw
Bit 31 DIC: Disable interrupt on completion
When set, this bit prevents setting the Status register's RS bit (CSR5[6]) for the received frame
ending in the buffer indicated by this descriptor. This, in turn, disables the assertion of the interrupt to
Host due to RS for that frame.
Bits 30:29 Reserved
Bits 28:16 RBS2: Receive buffer 2 size
These bits indicate the second data buffer size, in bytes. The buffer size must be a multiple of 4, 8,
or 16, depending on the bus widths (32, 64 or 128, respectively), even if the value of RDES3
(buffer2 address pointer) is not aligned to bus width. If the buffer size is not an appropriate multiple of
4, 8 or 16, the resulting behavior is undefined. This field is not valid if RDES1 [14] is set.
Bit 15 RER: Receive end of ring
When set, this bit indicates that the descriptor list reached its final descriptor. The DMA returns to the
base address of the list, creating a descriptor ring.
Bit 14 RCH: Second address chained
When set, this bit indicates that the second address in the descriptor is the next descriptor address
rather than the second buffer address. When this bit is set, RBS2 (RDES1[28:16]) is a "don't care"
value. RDES1[15] takes precedence over RDES1[14].
Bit 13 Reserved
Bits 12:0 RBS1: Receive buffer 1 size
Indicates the first data buffer size in bytes. The buffer size must be a multiple of 4, 8 or 16,
depending upon the bus widths (32, 64 or 128), even if the value of RDES2 (buffer1 address pointer)
is not aligned. When the buffer size is not a multiple of 4, 8 or 16, the resulting behavior is undefined.
If this field is 0, the DMA ignores this buffer and uses Buffer 2 or next descriptor depending on the
value of RCH (bit 14).
RDES2: Receive descriptor Word2
RDES2 contains the address pointer to the first data buffer in the descriptor.
31 30 29 28 27 26 25
rw rw rw rw rw rw rw
Bits 31:0 RBAP1: Receive buffer 1 address pointer
These bits indicate the physical address of Buffer 1. There are no limitations on the buffer address
alignment except for the following condition: the DMA uses the configured value for its address
generation when the RDES2 value is used to store the start of frame. Note that the DMA performs a
write operation with the RDES2[3/2/1:0] bits as 0 during the transfer of the start of frame but the frame
data is shifted as per the actual Buffer address pointer. The DMA ignores RDES2[3/2/1:0]
(corresponding to bus width of 128/64/32) if the address pointer is to a buffer where the middle or
last part of the frame is stored.
878/959
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
RBS2
rw rw rw rw rw rw rw rw rw rw rw
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
rw rw rw rw rw rw rw rw rw rw rw rw rw
RBP1
9 8 7 6 5 4 3 2
RBS
9 8 7 6 5 4 3 2
RM0034
1 0
1 0