Fractional Baud Rate Generation - ST STM32F101xx Reference Manual

RM0034
When the framing error is detected:
●
The FE bit is set by hardware
● The invalid data is transferred from the Shift register to the USART_DR register.
●
No interrupt is generated in case of single byte communication. However this bit rises
at the same time as the RXNE bit which itself generates an interrupt. In case of
multibuffer communication an interrupt will be issued if the EIE bit is set in the
USART_CR3 register.
The FE bit is reset by a USART_SR register read operation followed by a USART_DR
register read operation.
Configurable stop bits during reception
The number of stop bits to be received can be configured through the control bits of Control
Register 2 - it can be either 1 or 2 in normal mode and 0.5 or 1.5 in Smartcard mode.
1. 0.5 stop Bit (reception in Smartcard mode): No sampling is done for 0.5 stop bit. As
a consequence, no framing error and no break frame can be detected when 0.5 stop bit
is selected.
2. 1 stop Bit: Sampling for 1 stop Bit is done on the 8th, 9th and 10th samples.
3. 1.5 stop Bits (transmission in Smartcard mode): When transmitting in smartcard
mode, the device must check that the data is correctly sent. Thus the receiver block
must be enabled (RE =1 in the USART_CR1 register) and the stop bit is checked to test
if the smartcard has detected a parity error. In the event of a parity error, the smartcard
forces the data signal low during the sampling - NACK signal-, which is flagged as a
framing error. Then, the FE flag is set with the RXNE at the end of the 1.5 stop bit.
Sampling for 1.5 stop bits is done on the 16th, 17th and 18th samples (1 baud clock
period after the beginning of the stop bit). The 1.5 stop bit can be decomposed into 2
parts: one 0.5 baud clock period during which nothing happens, followed by 1 normal
stop bit period during which sampling occurs halfway through. Refer to
Smartcard on page 666
4. 2 stop Bits: Sampling for 2 stop bits is done on the 8th, 9th and 10th samples of the
first stop bit. If a framing error is detected during the first stop bit the framing error flag
will be set. The second stop bit is not checked for framing error. The RXNE flag will be
set at the end of the first stop bit.
25.3.4

Fractional baud rate generation

The baud rate for the receiver and transmitter (Rx and Tx) are both set to the same value as
programmed in the Mantissa and Fraction values of USARTDIV.
USARTDIV is an unsigned fixed point number that is coded on the USART_BRR register.
How to derive USARTDIV from USART_BRR register values
Example 1:
If DIV_Mantissa = 27d and DIV_Fraction= 12d (USART_BRR=1BCh), then
Mantissa (USARTDIV) = 27d
Universal synchronous asynchronous receiver transmitter (USART)
for more details.
f
Tx/ Rx baud =
(16*USARTDIV)
legend: f - Input clock to the peripheral (PCLK1 for USART2, 3, 4, 5 or PCLK2 for USART
PCLKx(x=1,2)
CK
Section 25.3.10:
657/959