ST STM32F101xx Reference Manual page 851

RM0034
be greater than or equal to the resolution of time stamp counter. The synchronization
accuracy target between the master node and the slaves is around 100 ns.
The generation, update and modification of the System Time are described in the
System Time correction
The accuracy depends on the PTP reference clock input period, the characteristics of the
oscillator (drift) and the frequency of the synchronization procedure.
Due to the synchronization from the Tx and Rx clock input domain to the PTP reference
clock domain, the uncertainty on the time stamp latched value is 1 reference clock period. If
we add the uncertainty due to resolution, we will add half the period for time stamping.
Transmission of frames with the PTP feature
When a frame's SFD is output on the MII, a time stamp is captured. Frames for which time
stamp capture is required are controllable on a per-frame basis. In other words, each
transmitted frame can be marked to indicate whether a time stamp must be captured or not
for that frame. The transmitted frames are not processed to identify PTP frames. Frame
control is exercised through the control bits in the transmit descriptor (as described in
Figure 315: Transmit descriptor field format with IEEE1588 time stamp enabled on
page 868). Captured time stamps are returned to the application in the same way as the
status is provided for frames. The time stamp is sent back along with the Transmit status of
the frame, inside the corresponding transmit descriptor, thus connecting the time stamp
automatically to the specific PTP frame. The 64-bit time stamp information is written back to
the TDES2 and TDES3 fields, with TDES2 holding the time stamp's 32 least significant bits
as described in
Reception of frames with the PTP feature
When the IEEE 1588 time stamping feature is enabled, the Ethernet MAC captures the time
stamp of all frames received on the MII. The received frames are not processed to identify
PTP frames. The MAC provides the time stamp as soon as the frame reception is complete.
Captured time stamps are returned to the application in the same way as the frame status is
provided. The time stamp is sent back along with the Receive status of the frame, inside the
corresponding receive descriptor. The 64-bit time stamp information is written back to the
RDES2 and RDES3 fields, with RDES2 holding the time stamp's 32 least significant bits as
described in
System Time correction methods
The 64-bit PTP time is updated using the PTP input reference clock, HCLK. This PTP time is
used as a source to take snapshots (time stamps) of the Ethernet frames being transmitted
or received at the MII. The System Time counter can be initialized or corrected using either
the Coarse or the Fine correction method.
In the Coarse correction method, the initial value or the offset value is written to the Time
stamp update register (refer to
page 902). For initialization, the System Time counter is written with the value in the Time
stamp update registers, whereas for system time correction, the offset value (Time stamp
update register) is added to or subtracted from the system time.
In the Fine correction method, the slave clock (reference clock) frequency drift with respect
to the master clock (as defined in IEEE 1588) is corrected over a period of time, unlike in the
Coarse correction method where it is corrected in a single clock cycle. The longer correction
time helps maintain linear time and does not introduce drastic changes (or a large jitter) in
Ethernet (ETH): media access control (MAC) with DMA controller
methods.
Tx DMA descriptor format with IEEE1588 time stamp on page
Rx DMA descriptors format with IEEE1588 time stamp on page
Section 28.8.3: IEEE 1588 time stamp registers on
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