Table 199. Flexible Trace Pin Assignment - ST STM32F101xx Reference Manual

RM0034
TPUI TRACE pin assignment
By default, these pins are NOT assigned. They can be assigned by setting the IOTRACEN
and IOTRACEMODE bits of the MCU Debug Component Configuration Register. This
configuration has to be done by the debugger host.
In addition, the number of pins to assign depends on the trace configuration (asynchronous
or synchronous).
Asynchronous mode: 1 extra pin is needed
Synchronous mode: from 2 to 5 extra pins are needed depending on the size of the
data trace port register (1, 2 or 4):
–
–
–
–
–
To assign the TRACE pin, the debugger host must program the bits TRACE_IOEN and
TRACE_MODE[1:0] of the Debug MCU configuration Register (DBGMCU_CR). By default
the TRACE pins are not assigned.
This register is mapped on the external PPB and is reset by the PORESET (and not by the
SYSTEM reset). It can be written by the debugger under SYSTEM reset.

Table 199. Flexible TRACE pin assignment

DBGMCU_CR
register
0
1
1
1
1
(1)
When Serial Wire mode is used, it is released. But when JTAG is used, it is assigned to JTDO.
Note: By default, the TRACECLKIN input clock of the TPIU is tied to GND. It is assigned to HCLK
two clock cycles after the bit TRACE_IOEN has been set.
TRACECK
TRACED(0) if port size is configured to 1, 2 or 4
TRACED(1) if port size is configured to 2 or 4
TRACED(2) if port size is configured to 4
TRACED(3) if port size is configured to 4
Pins assigned for:
No Trace (default
XX
state)
00 Asynchronous Trace
Synchronous Trace
01
1 bit
Synchronous Trace
10
2 bit
Synchronous Trace
11
4 bit
TRACE I/O pin assigned
PB3 /
PE2 / PE3 /
JTDO/
TRACE TRACE
TRACES
CK D[0]
WO
Released
(1)
TRACES
WO
TRACE TRACE
CK D[0]
Released TRACE TRACE
(1)
CK D[0]
TRACE TRACE
CK D[0]
Debug support (DBG)
PE4 / PE5 / PE6 /
TRACE TRACE TRACE
D[1] D[2] D[3]
Released
(usable as GPIO)
TRACE
D[1]
TRACE TRACE TRACE
D[1] D[2] D[3]
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