ST STM32F101xx Reference Manual page 711

RM0034
Bit 7 GONAKEFF: Global OUT NAK effective
Indicates that the Set global OUT NAK bit in the Device control register (SGONAK bit in
OTG_FS_DCTL), set by the application, has taken effect in the core. This bit can be cleared by
writing the Clear global OUT NAK bit in the Device control register (CGONAK bit in
OTG_FS_DCTL).
Note: Only accessible in Device mode.
Bit 6 GINAKEFF: Global IN non-periodic NAK effective
Indicates that the Set global non-periodic IN NAK bit in the Device control register (SGINAK bit
in OTG_FS_DCTL), set by the application, has taken effect in the core. That is, the core has
sampled the Global IN NAK bit set by the application. This bit can be cleared by clearing the
Clear global non-periodic IN NAK bit in the Device control register (CGINAK bit in
OTG_FS_DCTL).
This interrupt does not necessarily mean that a NAK handshake is sent out on the USB. The
STALL bit takes precedence over the NAK bit.
Note: Only accessible in Device mode.
Bit 5 Reserved.
Bit 4 RXFLVL: RxFIFO non-empty
Indicates that there is at least one packet pending to be read from the RxFIFO.
Note: Accessible in both Host and Device modes.
Bit 3 SOF: Start of frame
In Host mode, the core sets this bit to indicate that an SOF (FS), or Keep-Alive (LS) is
transmitted on the USB. The application must write a 1 to this bit to clear the interrupt.
In Device mode, in the core sets this bit to indicate that an SOF token has been received on
the USB. The application can read the Device Status register to get the current frame number.
This interrupt is seen only when the core is operating in FS.
Note: Accessible in both Host and Device modes.
Bit 2 OTGINT: OTG interrupt
The core sets this bit to indicate an OTG protocol event. The application must read the OTG
Interrupt Status (OTG_FS_GOTGINT) register to determine the exact event that caused this
interrupt. The application must clear the appropriate status bit in the OTG_FS_GOTGINT
register to clear this bit.
Note: Accessible in both Host and Device modes.
Bit 1 MMIS: Mode mismatch interrupt
The core sets this bit when the application is trying to access:
A Host mode register, when the core is operating in Device mode
A Device mode register, when the core is operating in Host mode
The register access is completed on the AHB with an OKAY response, but is ignored by the
core internally and does not affect the operation of the core.
Note: Accessible in both Host and Device modes.
Bit 0 CMOD: Current mode of operation
Indicates the current mode.
0: Device mode
1: Host mode
Note: Accessible in both Host and Device modes.
USB on-the-go full-speed (OTG_FS)
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