Figure 306. Wakeup Frame Filter Register - ST STM32F101xx Reference Manual

RM0034
Remote wakeup frame filter register
There are eight wakeup frame filter registers. To write on each of them, load the wakeup
frame filter register value by value. The wanted values of the wakeup frame filter are loaded
by sequentially loading eight times the wakeup frame filter register. The read operation is
identical to the write operation. To read the eight values, you have to read eight times the
wakeup frame filter register to reach the last register. Each read/write points the wakeup
frame filter register to the next filter register.

Figure 306. Wakeup frame filter register

Wakeup frame filter reg0
Wakeup frame filter reg1
Wakeup frame filter reg2
Wakeup frame filter reg3
Wakeup frame filter reg4
Wakeup frame filter reg5
Wakeup frame filter reg6
Wakeup frame filter reg7
Filter i Byte Mask
This register defines which bytes of the frame are examined by filter i (0, 1, 2, and 3) in
order to determine whether or not the frame is a wakeup frame. The MSB (thirty-first
bit) must be zero. Bit j [30:0] is the Byte Mask. If bit j (byte number) of the Byte Mask is
set, then Filter i Offset + j of the incoming frame is processed by the CRC block;
otherwise Filter i Offset + j is ignored.
Filter i Command
This 4-bit command controls the filter i operation. Bit 3 specifies the address type,
defining the pattern's destination address type. When the bit is set, the pattern applies
to only multicast frames. When the bit is reset, the pattern applies only to unicast
frames. Bit 2 and bit 1 are reserved. Bit 0 is the enable bit for filter i; if bit 0 is not set,
filter i is disabled.
Filter i Offset
This register defines the offset (within the frame) from which the frames are examined
by filter i. This 8-bit pattern offset is the offset for the filter i first byte to be examined.
The minimum allowed is 12, which refers to the 13th byte of the frame (offset value 0
refers to the first byte of the frame).
Filter i CRC-16
This register contains the CRC_16 value calculated from the pattern, as well as the
byte mask programmed to the wakeup filter register block.
Remote wakeup frame detection
When the MAC is in sleep mode and the remote wakeup bit is enabled in the
ETH_MACPMTCSR register, normal operation is resumed after receiving a remote wakeup
frame. The application writes all eight wakeup filter registers, by performing a sequential
Ethernet (ETH): media access control (MAC) with DMA controller
Filter 3
RSVD RSVD
Command
Filter 3 Offset Filter 2 Offset
Filter 1 CRC - 16
Filter 3 CRC - 16
Filter 0 Byte Mask
Filter 1 Byte Mask
Filter 2 Byte Mask
Filter 3 Byte Mask
Filter 2 Filter 1
RSVD
Command Command
Filter 1 Offset
Filter 0 CRC - 16
Filter 2 CRC - 16
Filter 0
RSVD
Command
Filter 0 Offset
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