ST STM32F101xx Reference Manual page 90

Low-, medium- and high-density reset and clock control (RCC)
Bit 22 I2C2RST: I2C 2 reset
Bit 21 I2C1RST: I2C 1 reset
Bit 20 UART5RST: USART 5 reset
Bit 19 UART4RST: USART 4 reset
Bit 18 USART3RST: USART 3 reset
Bit 17 USART2RST: USART 2 reset
Bits 16
Bit 15 SPI3RST: SPI 3 reset
Bit 14 SPI2RST: SPI 2 reset
Bits 13:12
Bit 11 WWDGRST: Window watchdog reset
Bits 10:6
Bit 5 TIM7RST: Timer 7 reset
90/959
Set and cleared by software.
0: No effect
1: Reset I2C 2
Set and cleared by software.
0: No effect
1: Reset I2C 1
Set and cleared by software.
0: No effect
1: Reset USART 5
Set and cleared by software.
0: No effect
1: Reset USART 4
Set and cleared by software.
0: No effect
1: Reset USART 3
Set and cleared by software.
0: No effect
1: Reset USART 2
Reserved, always read as 0.
Set and cleared by software.
0: No effect
1: Reset SPI 3
Set and cleared by software.
0: No effect
1: Reset SPI 2
Reserved, always read as 0.
Set and cleared by software.
0: No effect
1: Reset window watchdog
Reserved, always read as 0.
Set and cleared by software.
0: No effect
1: Reset timer 7
RM0034