Master Device Processing
(Transmission Side)
Program
CMDT
Setting
Processing
Hardware
Operation
Transfer Line
SCK Pin
SB0 Pin
Slave Device Processing
(Reception Side)
Program
Processing
Hardware
CMDD
Operation
Setting
Fig. 5-49 Address Transmission form Master Device to Slave Device (WUP = 1)
Write
RELT
CMDT
Setting
Setting
to SIO
Serial Transmit Operation
1
2
3
A7
A6
A5
CMDD
CMDD
Serial Receive Operation
Clear-
Setting
ance
RELD
Setting
IRQCSI
Gene-
ration
4
5
6
7
8
9
A4
A3
A2
A1
A0
Address
IRQCSI
Gene-
ration
(When SVA = SIO)
Interrupt Servicing
(Preparation for Next Serial Transfer)
ACKD
Setting
ACK
BUSY
BUSY
ACKT
WUP
0
Clear-
Setting
ance
BUSY
BUSY
ACK
Clear-
Output
Output
ance
SCK
Stop-
page
READY