Migration Differences; Port Widths And Byte Mapping; Crc; Comma Alignment - Xilinx RocketIO X User Manual

Migration Differences

Migration Differences
The following is a list of differences that must be considered when migrating a design from
using RocketIO transceivers to using RocketIO X transceivers.

Port Widths and Byte Mapping

All ports that are byte mapped are 8 bits wide instead of 4 bits wide as in RocketIO X
transceivers to support up to 8 bytes or eight 10-bit words at the data interface. The
mapping is the same. For instance, RXCHARISK[0] denotes if RXDATA[7:0] is a K-
character; RXCHARISK[1] denotes if RXDATA[15:8] is a K-character, etc.

CRC

There is no CRC functionality built into the RocketIO X transceiver. CRC must be done in
the fabric if required. Xilinx Application Note,
in the FPGA fabric.

Comma Alignment

The attribute ALIGN_COMMA_MSB is replaced by the attribute
ALIGN_COMMA_WORD. It can be set to 1, 2, and 4. The RocketIO transceiver required a
circuit for aligning the RXDATA on 4-byte boundaries. With the RocketIO X transceiver
that functionality can be accomplished by setting ALIGN_COMMA_WORD to 4.
The ENPCOMMAALIGN and ENMCOMMAALIGN are now synchronous to
RXUSRCLK2. There is no need to clock them with a register in the RXRECCLK domain as
there was with the RocketIO transceiver.
The PCOMMA_10B_VALUE, MCOMMA_10B_VALUE, and COMMA_10B_MASK
attributes are bit swapped. For instance, with the RocketIO transceiver, to set the comma
value to positive K28.5 one sets PCOMMA_10B_VALUE = 0011111010. With the
RocketIO X transceiver one sets PCOMMA_10B_VALUE = 0101111100.
Port RXCOMMADETUSE is added and must be asserted High to enable comma
alignment.

Reference Clocking

BREFCLKPIN and BREFCLKNIN pins can only be routed to all transceivers on one side of
the chip.

Clocking and Data Width

TXUSRCLK/TXUSERCLK2 and RXUSRCLK/RXUSRCLK2 have the same phase and ratio
dependence on the data path width as in the RocketIO transceiver.
TXOUTCLK is a new port that is derived from the BREFCLK or REFCLK input. This signal
can be routed to a DCM to produce the USRCLKs. The TXOUTCLK can be set to be a
divided version of the reference clock for use in 64B/66B applications. BREFCLK or
REFCLK can still be routed directly to a DCM or BUFGMUX as with the RocketIO
transceiver.
Ports for data width have been added. RXDATAWIDTH/TXDATAWIDTH replace the
TX_DATA_WIDTH and RX_DATA_WIDTH attributes from the RocketIO transceiver.
RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004
XAPP209
www.xilinx.com
1-800-255-7778
describes how to implement CRC
R
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