Unused Reference Clocks; Reference Clock Output Buffer; Reference Clock Power; Power Supply And Filtering - Xilinx Virtex UltraScale+ FPGAs User Manual

Unused Reference Clocks

If the reference clock input is not used, leave the reference clock input pins unconnected (both
MGTREFCLKP and MGTREFCLKN).

Reference Clock Output Buffer

The reference clock pins can be configured to be output pins that drive an RX recovered clock
from one of the transceivers in the Dual. Operation and configuration of this buffer is discussed
in Chapter 2: Shared
capacitors on the PCB. The signal levels are comparable to those of LVDS after the DC blocking
capacitors. See the UltraScale+ device data sheets (see
for output levels.

Reference Clock Power

The GTM transceiver reference clock input circuit is powered by MGTAVCC. Excessive noise on
this supply has a negative impact on the performance of any GTM transceiver Dual that uses the
reference clock from this circuit.

Power Supply and Filtering

The GTM transceiver Dual requires three analog power supplies: MGTAVCC at a nominal voltage
level of 0.85 VDC or 0.9 VDC for UltraScale+ FPGAs, MGTVCCAUX at a nominal voltage level of
1.8 VDC, VCCINT_GT at a nominal voltage of 0.85 VDC, and MGTAVTT at a nominal voltage
level of 1.2 VDC. The pins for each of these analog power supplies are tied to a plane in the
package. In some packages, there are two planes (a north plane and a south plane) for each of the
analog power supplies. See
planes in the GTM transceiver packages.
Noise on the GTM transceiver analog power supplies can cause degradation in the performance
of the transceivers. The most likely form of degradation is an increase in jitter at the output of
the GTM transmitter and reduced jitter tolerance in the receiver. Sources of power supply noise
are:
• Power supply regulator noise
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
Features. This output is designed to supply a signal through DC blocking
Analog Power Supply Pins
Chapter 5: Board Design Guidelines
http:/ /www.xilinx.com/documentation)
for a discussion of the internal power
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