Chapter 1: Virtex-5 Fpga Gtp Transceiver Ibis-Ami Sis Kit; Introduction; Release Notes For The Gtp Transceiver Sis Kit - Xilinx virtex-5 fpga User Manual

Virtex-5 FPGA GTP Transceiver
IBIS-AMI SIS Kit

Introduction

This document provides a complete overview of the Virtex®-5 FPGA RocketIO™ GTP
Transceiver IBIS-AMI Signal Integrity Simulation (SIS) Kit, including block diagrams,
system configurations, transfer nets, and libraries. It explains how to install the SIS kit and
the associated files, gives an overview of the SIS kit file hierarchy, and describes the steps
for getting started with simulations.
The Quantum Channel Designer from Signal Integrity Software, Inc. (SiSoft) was used to
simulate the models and example channels. With SiSoft's Quantum Channel Designer
(QCD), designers can quickly implement and validate high-speed serializer/deserializer
interfaces for bit error rate (BER) and eye-mask compliance.
Quantum Channel Designer/IBIS-AMI Correlation
Channel Designer IBIS-AMI simulation results were correlated with the HSPICE
simulations. Results are documented with waveform plots.
Additional information on the models, ports, and options can be obtained from UG196,
Virtex-5 FPGA RocketIO GTP Transceiver User Guide. Additional information regarding the
Quantum Channel Designer can be obtained from the SiSoft Quantum Channel Designer
User Guide (provided with the SIS Kit installation). Questions regarding Quantum Channel
Designer should be directed to SiSoft.

Release Notes for the GTP Transceiver SIS Kit

Table 1-1
version.
Table 1-1: Document and SIS Kit Version Correlation
The TX and RX models are created to be used primarily in an AC-coupled environment.
Virtex-5 FPGA GTP Transceiver SIS Kit (IBIS-AMI)
UG587 (v1.1) June 21, 2012
shows the UG587 document version and the associated GTP Transceiver SIS Kit
UG587 Version
1.0
1.1
www.xilinx.com
Appendix A, HSPICE and
Results, describes how the Quantum
SIS Kit Version
2.2
2.2
Chapter 1
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