Tx Interface - Xilinx Virtex UltraScale+ FPGAs User Manual

TX Interface

The TX interface is the gateway to the TX datapath of the GTM transceiver. Applications
transmit data through the GTM transceiver by writing data to the TXDATA port on the positive
edge of TXUSRCLK2. Port widths can be 64 and 128 bits for NRZ mode, or 80, 128, 160, and
256 bits for PAM4 mode. The rate of the parallel clock (TXUSRCLK2) at the interface is
determined by the TX line rate and the width of the TXDATA port. A second parallel clock
(TXUSRCLK) must be provided for the internal PCS logic in the transmitter. This section shows
how to drive the parallel clocks and explains the constraints on those clocks for correct
operation.
Interface Width Configuration
The GTM transceiver contains a 64-bit internal datapath in NRZ mode and an 80-bit and 128-bit
internal datapath in PAM4 mode that is configurable by setting the TX_INT_DATA_WIDTH
attribute. When the FEC is enabled, only the 80-bit internal datapath may be used. The interface
width is configurable by setting the TX_DATA_WIDTH attribute. In NRZ mode,
TX_DATA_WIDTH can be configured to 64 or 128 bits. In PAM4 mode, TX_DATA_WIDTH can
be configured to 80, 128, 160, or 256 bits. When the FEC is enabled, only the 80-bit or 160-bit
data width can be selected.
The following table shows how the interface width for the TX datapath is selected.
Table 28: TX Interface Datapath Configuration
Encoding FEC Allowed?
NRZ
NRZ
PAM4
PAM4
PAM4
PAM4
The following figure shows how the TX data is transmitted.
UG581 (v1.0) January 4, 2019
Virtex UltraScale+ GTM Transceivers
TX_DATA_WIDTH
Encoding
No 0
No 2
Yes 1
Yes 3
No 2
No 4
TX Data Width TX_INT_DATA_WI
Selection DTH Encoding
64
128
80
160
128
256
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Chapter 3: Transmitter
TX Internal
Datapath
Selection
0 64
0 64
1 80
1 80
2 128
2 128
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