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11.3 Technical Description Input Selector 1 & 2
11.3.1 Technical Description Input Selector 1
11.3.1.1 General Description
General description
The full input section comprises two (-cable fixed BNC inputs and two digital slots to insert (optional) digital modules like the SDI /
H-SDI or another digital decoder. On input 1 there is also a DVI / OUT available and input 2 has a DVI IN only. A digital decoder
R763826 is connected to each of the input boards. Video or S-video signals are processed in this digital decoder board to re-enter
this input board where they are buffered in order to add them to the digital RGB_ ANA1 bus.
The RGB computer input signals are converted into a 48-bit (3x2x8) digital RGB format. They are then multiplexed together with
three other 48 digital RGB channels onto two 48-bit digital RGB outputs for the Pixel Map Processor.
Besides signal processing, the board also handles the sync processing and multiplexing (=selection) of the sync for the AMDS
(source identification) on the PMP.
The 5-cable input can handle all possible analog input signals: RGBHV, RGBCS, RGBCV, RGsB, YUVCS, YsUV, video and S-video.
The RGB and YUV signals are sent to an ADC (Analog to Digital Converter).
1
The PanelLink*
or DVI input allows a direct digital interfacing with a DVI output of a PC card or other devices equipped with DVI
outputs, such as scalers.
The PanelLink* signals are also processed by a DVI receiver chip set. An FPGA is then programmed for re-syncing and deliver an
output to the RGB ANA1 digital bus and to the transmitter DVI chipset for loop through purposes. The same transmitter chip set also
can receive the DVI signal from the PMP board via a buffer.
In case of a PanelLink input, the resolution of the projector's display device must match the resolution of the graphics card of the
PC. This means that the native resolution of the DMD panel of the projector must be communicated to the graphics card (or scaler)
through the DVI connector. This information is stored and is available in an E²PROM on the Input Selector 1. The DVI source can
access and read this info via a kind of I²C bus. This communication link is called Display Data Channel (DDC).
This bus can also be switched to the controller I²C bus of the FPGA on the input selector 1 for programming or updating later.
The DVI output has mainly as task to loop through two or three projectors. This DVI output signal can be either the looped DVI input
signal, or the processed RGB input signal (processed already by the PMP).
This PannelLink output is a signal that has already been processed and does in theory not need further processing in the PMP of
the slaved projector, except for the OSD information.
This means that ALL resolution image processing like edge or contrast enhancement, PIP, etc.., are present in the output signal.
However, due to tolerances in the looped projectors some small corrections on black level and gain may be required.
11.3.1.2 Detailed description (see schematics sheet 1/11 to 11/11
11.3.1.2.1 Analog Input and sync processing.
1. Signal selection (sheet 1/11).
The "INTERCONNECTION DIAGRAM" shows a "Power Backplane" (R763426) and an "Input Backplane " (R763378).
The "Power Backplane" is a power interface module for distributing the power from the SMPS to different boards.
The "Input Backplane" is an interface for the signals, receiving the two input selector 1 and 2 signals, the communication Interface
and the CPU (I²C bus).
The RGB inputs are correctly terminated with 75 Ohm and the R/G/B_IN1 signals proceed to the ADC Analog to Digital Converter I4
via clamping capacitors. The RED_DEC1, BLUE_DEC1, CHROM_DEC1 and Y/CVBS_DEC1 signals proceed to the digital decoder
via connector J3.
2. Sync selection
Sync pulses embedded in video signals can either be applied to the G input (Sync on Green) or to the HS/CS/CV input (compos-
ite video with RGB signals at standard 15kHz). The selection happens based upon the lines YS_1_SEL for sync on green and
HS/CS_1_SEL for a composite video sync. The user in the installation menu must do this selection. Disturbing video frequencies
are filtered out with C3 by switching on Q1.
SOG_IN1 goes to the ADC whereas SYNC_DEC proceeds to the digital decoder for 15kHz component inputs.
1. (*)PanelLink is a trademark of Silicon Image. PanelLink provides a high-speed serial interface that is consistent from VGA through UXGA panel technologies is highly skew and jitter
tolerant and can be AC coupled. The standardization of the data mapping according to Digital Visual Interface (DVI) standard makes the interface even more powerful since it allows
displays and systems from different manufacturers to inter-operate with each other seamlessly.
R5976820 SLM R12+ PERFORMER 08/03/2005
11. Signal Input Selection R763850 & R763851
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