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21.3 Short Technical Description
Data Path
Digital RGB data coming form input selector 1 enters the PMP where the data is stored in an SDRAM frame memory. Therefore an
SDRAM controller is needed and this controller is implemented in a Xilinx programmable component. Also, the horizontal conversion
to the native resolution is done in this component.
Data is vertically converted to the native resolution in an Altera that also contains the deinterlacer.
Then the data is processed for video enhancements in a second Altera. Also the On Screen Display is inserted in this second Altera.
After conversion and video processing, the data is sent to the formatter board.
Controlling the board
In order to do the pixel mapping properly, there is need of some control functions. Some important functions are:
AMDS
The Automatic Mode Detection and Synchronization circuit detects the source applied to the projector.
OSD
A character flash and a SDRAM device are connected to the controller. The flash contains the shapes of each possible character,
while the SDRAM contains the codes of the characters that needs to be shown on the screen. The controller sends the result to
Altera's for insertion.
Processor Interface
A processor interface is implemented in order to be able to communicate with the main processor board. The main processor sends
its data through the processor interface to the different components on the board or to internal control registers.
Clock Circuit
The main clock circuit consists of crystal oscillators and some clock buffers and multipliers.
Power Supply
3.3V is supplied directly to the board, which eliminates a 3.3V power supply. Two switch modes convert the 3.3V in to 1.8V and 2.5V.
Software Adjustments
•
Geometry parameters: All geometry settings are done on the Pixel Map Processor:
•
Noise reduction: Signals are motion adaptive temporarily filtered dependent on a non-linear transform of their spectral energy
distribution.
21.4 Power Supply
Introduction
The PMP module receives the +3.3V power voltage from the SM Power supply. For the low voltage logic on board, two low power
voltages, a +1.8V and a 2.5V, are generated using each a step-down switching regulator controller (see schematics: sheet 9).
The +2.5V is applied to the Xilinx I400 whereas the +1.8V is applied to the Altera's I500, I100 and the Xilinx's I205, I305.
SM Power Supply
Image 21-3
Power Supply
R5976820 SLM R12+ PERFORMER 08/03/2005
+3.3V
R763418
21. Pixel Map Processor Module R764115
PMP R763348
3.3V Input High
Alterea I500
Power Step-Down
+1.8V
Alterea I100
Controller
Xilinx I205
IC600
Xilinx I305
3.3V Input High
Power Step-Down
+2.5V
Switching Regulator
Xilinx I400
Controller
IC650
159
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