Cfeb - Juniper M10i Hardware Manual

M10i Multiservice Edge Router Hardware Guide

CFEB

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Figure 5: CFEB
The CFEB has the following major components:
Processing components:
266-MHz CPU and supporting circuitry
Integrated ASIC
33-MHz PCI bus
Storage components:
128-MB SDRAM for packet memory
128-MB SDRAM for the microkernel
8-MB SSRAM for route lookup
4-MB SSRAM for control memory
System interfaces:
100-Mbps Ethernet link for internal interface to the Routing Engine
19.44-MHz reference clock that generates clock signal for SONET/SDH PICs
I2C controller to read the I2C/EEPROMs in the PICs and temperature sensors
I2C/EEPROM containing the serial number and revision level
Two 512-KB boot flash EPROMs (programmable on the board)
One PowerPC 8245 integrated processor
Three LEDs—A green LED labeled
indicate CFEB status. .
MASTER
Online/Offline button—Prepares the CFEB for removal from the router when pressed.
Ejector levers—Control the locking system that secures the CFEB in the chassis.
, a red LED labeled
OK FAIL
Copyright © 2010, Juniper Networks, Inc.
, and a blue LED labeled