Control Status Register (Csr); Control Status Register Field Descriptions - Texas Instruments TMS320C6000 Series Reference Manual

2.6.2

Control Status Register (CSR)

Figure 2–5. Control Status Register (CSR)
Table 2–6. Control Status Register Field Descriptions
Bit Position Width
31-24 8
23-16 8
15-10 6
9 1
8 1
7-5 3
4-2 3
1 1
0 1
† See the TMS320C6201/C6701 Peripherals Reference Guide for more information.
The CSR, shown in Figure 2–5, contains control and status bits. The functions
of the fields in the CSR are shown in Table 2–6. For the EN, PWRD, PCC, and
DCC fields, see your data sheet to see if your device supports the options that
these fields control and see the TMS320C6201/C6701 Peripherals Reference
Guide for more information on these options.
31
CPU ID
15
PWRD
R, W, +0
Legend: R Readable by the MVC instruction
W Writeable by the MVC instruction
+x Value undefined after reset
+0 Value is zero after reset
C Clearable using the MVC instruction
Field Name Function
CPU ID CPU ID; defines which CPU.
CPU ID = 00b: indicates 'C62x, CPU ID= 10b: indicates 'C67x
Revision ID Revision ID; defines silicon revision of the CPU
PWRD Control power-down modes; the values are always read as zero.
SAT The saturate bit, set when any unit performs a saturate, can be
cleared only by the MVC instruction and can be set only by a func-
tional unit. The set by a functional unit has priority over a clear (by
the MVC instruction) if they occur on the same cycle. The saturate
bit is set one full cycle (one delay slot) after a saturate occurs. This
bit will not be modified by a conditional instruction whose condition
is false.
EN Endian bit: 1 = little endian, 0 = big endian
PCC Program cache control mode
DCC Data cache control mode
PGIE Previous GIE (global interrupt enable); saves GIE when an inter-
rupt is taken
GIE Global interrupt enable; enables (1) or disables (0) all interrupts
except the reset interrupt and NMI (nonmaskable interrupt)
TMS320C62x/C67x Control Register File
24 23
R
10 9 8 7
SAT EN PCC
R, C, +0 R, +x
†
†
CPU Data Paths and Control
Revision ID
1
5 4 2
DCC PGIE GIE
R, W, +0
†
16
0
†
2-11