Timing Registers; Xrevision Register; Xintf Configuration And Control Register Mappings; Xrevision Register Bit Definitions - Texas Instruments TMS320C2810 Data Manual

www.ti.com
The operation and timing of the external interface, can be controlled by the registers listed in
Table 3-10. XINTF Configuration and Control Register Mappings
NAME ADDRESS
XTIMING0 0x00 0B20
XTIMING1 0x00 0B22
XTIMING2 0x00 0B24
XTIMING6 0x00 0B2C
XTIMING7 0x00 0B2E
XINTCNF2 0x00 0B34
XBANK 0x00 0B38
XREVISION 0x00 0B3A

3.5.1 Timing Registers

XINTF signal timing can be tuned to match specific external device requirements such as setup and hold
times to strobe signals for contention avoidance and maximizing bus efficiency. The XINTF timing
parameters can be configured individually for each zone based on the requirements of the memory or
peripheral accessed by that particular zone. This allows the programmer to maximize the efficiency of the
bus on a per-zone basis. All XINTF timing values are with respect to XTIMCLK, which is equal to or one-
half of the SYSCLKOUT rate, as shown in
For detailed information on the XINTF timing and configuration register bit fields, see the TMS320x281x
DSP External Interface (XINTF) Reference Guide (literature number SPRU067).

3.5.2 XREVISION Register

The XREVISION register contains a unique number to identify the particular version of XINTF used in the
product. For the 2812, this register will be configured as described in
BIT(S) NAME
15–0 REVISION
Copyright © 2001–2012, Texas Instruments Incorporated
Product Folder Link(s):
SIZE
(x16)
2 XINTF Timing Register, Zone 0 can access as two 16-bit registers or one 32-bit register.
2 XINTF Timing Register, Zone 1 can access as two 16-bit registers or one 32-bit register.
2 XINTF Timing Register, Zone 2 can access as two 16-bit registers or one 32-bit register.
2 XINTF Timing Register, Zone 6 can access as two 16-bit registers or one 32-bit register.
2 XINTF Timing Register, Zone 7 can access as two 16-bit registers or one 32-bit register.
2 XINTF Configuration Register can access as two 16-bit registers or one 32-bit register.
1 XINTF Bank Control Register
1 XINTF Revision Register
Figure
Table 3-11. XREVISION Register Bit Definitions
TYPE RESET
R 0x0004
Submit Documentation Feedback
TMS320F2810 TMS320F2811 TMS320F2812 TMS320C2810 TMS320C2811 TMS320C2812
TMS320F2810, TMS320F2811, TMS320F2812
TMS320C2810, TMS320C2811, TMS320C2812
SPRS174T – APRIL 2001 – REVISED MAY 2012
DESCRIPTION
6-30.
Table
DESCRIPTION
Current XINTF Revision. For internal use/reference. Test purposes
only. Subject to change.
Table 3-10.
3-11.
Functional Overview 43